1. Field of the Invention
The present invention generally relates to memory systems utilizing memory components of the recirculating type which are operated selectively at fast and slow recirculating rates and, more particularly to such systems implemented with so called "partially good" memory components.
2. Description of the Prior Art
Memory systems of the recirculating type, for example, of the charge coupled device type, are well known. In an effort to minimize power dissipation of such memory systems, particularly where large numbers of memory cells are used in the same high density integrated circuit chips, only those chips selected for reading or writing purposes are recirculated at high rates. The unselected chips, at any given time, are recirculated at lower rates, consistent with data retention requirements, to minimize power dissipation and the associated chip cooling problems.
One concern that arises in the aforementioned memory systems is the avoidance of a reduction in the overall memory availability time. Due to the different recirculating rates of the selected and unselected memory components, said two components loose synchronization relative to each other with the selected devices undergoing a complete cycle of recirculation during the same time that the unselected devices undergo only a partial cycle of recirculation. It becomes necessary to provide additional time, after the selection mode (for reading or writing) has been completed to restore synchronization. Synchronization is regained by permitting the previously selected devices to continue to recirculate at a high rate until they "lap" (so to speak) the unselected devices and once again become time synchronized thereto. At that time, all devices are recirculated at the same low speed until the next memory access (selection mode) is desired. The next access can be postponed until resynchronization is achieved between all memory devices.
Alternatively, in order to increase the availability of the memory to a series of accesses, provision can be made for initiating a second access promptly following completion of the first access and without waiting for synchronization to be regained between the selected and unselected devices. This is made possible by the fact that the time phases of all the selected and non selected recirculating devices is known at all times. Therefore, access to a previously unselected device can be made promptly following completion of access to a selected device by keeping track of the known time phase of the recirculating bits of the former device upon completion of access to the latter device.
A further and more difficult problem arises when the memory system just described is implemented with "partially good" components (memory devices). Memory systems employing partially good components are described in U.S. Pat. Nos. 3,765,001, William F. Beausoleil, Issued Oct. 9, 1973, 3,781,826, William F. Beausoleil, Issued Dec. 25, 1973, and 3,845,476, Robert Francis Boehm, Issued Oct. 29, 1974, and assigned to the present assignee.
When a defective portion of a "partially good" component is addressed, it is replaced by a spare "all good" component which is provided for that purpose. Different portions of the same spare "all good" component can be used to replace the defective portions of many different "partially good" components. All portions of the "all good" spare components are always operated solely at the same recirculation rate. The entire "all good" chip is driven at a high clock rate when any portion thereof is selected. The entire "all good" chip is driven at a low clock rate when no portion thereof is selected. Thus, when the spare portion associated with one defective portion is driven at a high recirculation rate, the spare portion associated with all other defective portions are driven at the same high rate. In order to start a second memory access before "catch up" is completed following a first access, it would be necessary to map and store a listing of all the "partially good" components and which portion of each is defective. Such a mapping would constitute a considerable logic and storage investment.